1. Field
The present embodiments relate to a clock frequency dividing circuit generating clocks, and realizing a wide lock range and phase guarantee.
2. Description of the Related Art
In computer and communication fields, an amount of data processed has been recently increasing. In order to cope with the tendency toward an increase in data amount, an operation speed of Large Scale Integrated circuit (LSI) is becoming higher and a data transmission speed between LSIs is becoming higher.
Such speed-up and higher performance of communication and information processing devices are creating a demand for a transmission circuit transmitting/receiving high bit-rate signals and an operation circuit with high throughput. As a result, timing conditions imposed on clocks used in analog circuits and digital circuits realizing high-speed operation are becoming stricter.
As a typical clock frequency dividing circuit, a flip-flop (FF) circuit is known. A clock frequency dividing circuit using a FF circuit outputs a frequency dividing clock which synchronizes with an input clock when the input clock displaces. Generally, a frequency dividing circuit using a FF has a wideband characteristic and is often used in fields of relatively low frequencies of less than several GHz (see, for example, Japanese Unexamined Patent Application Publication No. H05-347554).
Further, in fields of a high frequency band ranging from several GHz to several tens GHz, there has been known a clock frequency dividing circuit using an injection lock technique which synchronizes an output clock of the frequency dividing circuit with its input clock. For example, in a document (A. Mazzanti, P. Uggetti and F. Svelto, “Analysis and Design of Injection-Locked LC Dividers for Quadrature Generation” IEEEJ. Solid-State Circuits, vol. 39, pp. 1425-1432, September 2004), a clock frequency circuit using the injection lock technique includes a LC oscillator made up of a coil (L) and a capacitor (C). Since a clock whose oscillation frequency is determined by values of L and C irrespective of an input clock (self-oscillation clock) is output, a frequency dividing clock synchronizing with the input clock is output by using the injection lock technique. The application of such a clock frequency dividing circuit in fields of a high frequency band ranging from several GHz to several tens GHz is expected, though it has a narrow band characteristic.
Generally, power consumption and output phase noise of a frequency dividing circuit using the injection lock technique are smaller than those of a frequency dividing circuit using a FF circuit. The reason for the low power consumption is that power consumption of a LC oscillator depends on power loss of a resistance component of the LC oscillator and this power loss is smaller than electrical charge and discharge in the FF circuit. The reason for the small output phase noise is its narrow band characteristic.
However, in the application in relatively low frequencies of less than several GHz, a required clock frequency is less than several GHz, and the use of the injection lock technique requires large values of L and C of the LC oscillator, which poses various problems in terms of size, cost, and the like. For this reason, a frequency dividing circuit using the injection lock technique has not been in wide use for a lower frequency band.
However, in accordance with the recent increase in throughput, high frequencies such as several GHz and several tens GHz have come into use, and the injection lock technique has been drawing attention as a technique realizing the generation and transmission of high-accuracy clocks.
In accordance with the recent speed-up and higher performance, timing restrictions imposed on clocks are becoming stricter. In particular, an increase in scale of LSI necessitates distribution of high-speed and high-accuracy clocks to various parts in the chip. However, in a conventional typical frequency dividing circuit using a FF circuit, it is difficult to reduce power consumption and output phase noise and so on.
A frequency dividing circuit using the injection lock technique, though drawing attention because of its small power consumption and output phase noise, has a problem of insufficient followability with input clocks in a wide frequency range because of its narrow band characteristic. A frequency dividing circuit using the injection lock technique is narrow in lock range which is a range of input clock frequencies with which its output clock can synchronize.
For example, when a clock output by a PLL is frequency-divided, there arises a problem that the lock range is not wide enough to cover a frequency range of the output clock of the PLL.
Thus, in using the injection lock technique realizing lower power consumption and small output phase noise, widening a lock range is a great problem to be solved for realizing its practical use.
Further, the frequency dividing circuit using the injection lock technique disclosed in the above-mentioned non-patent document has a problem that it is difficult to guarantee a phase relation of four-phase output clocks since the phase relation of the four-phase output clocks depends on an initial internal state and thus is not stable.